With increased integration and operation speed of semiconductor devices, new semiconductor device fabrication technologies are actively being studied. For high operation speed of semiconductor devices, it is required to minimize the length of a path along which electrons move when a transistor is turned on. To this end, studies of a short channel transistor whose channel length, which is the distance between a source and a drain of the transistor, is reduced are being carried out. In addition, studies regarding the use of salicide for minimizing contact resistance between the gate of the transistor and subsequent wires are being progressed.
FIG. 1 is a schematic diagram illustrating a configuration of a conventional semiconductor device. As shown in FIG. 1, a gate oxide film 102 and a gate poly 104 are formed in a device region of a semiconductor substrate 100, and a spacer 106 made of an insulation film is formed on a side wall of the gate poly 104. In addition, a Lightly Doped Drain (LDD) 108, in which impurities of a conductivity type opposite to a conductivity type of the semiconductor substrate 100 are lightly doped, is formed on the semiconductor substrate 100 under the gate oxide film 102. Source/drain regions 110 in which impurities of the same conductivity type as the LDD 108 are heavily doped are formed at a junction region of the semiconductor substrate 100 contacting with the LDD 108. In addition, a salicide film 112 for lowering contact resistance is formed on the gate poly 104 and the source/drain regions 110.
With the semiconductor device as configured above, for high operation speed of the transistor, the channel length between a source electrode and a drain electrode of the transistor should be reduced, as described above, and consequently, the width of the gate poly should be reduced. However, when the width of the gate poly is reduced, a serious narrow line effect may occur. Due to this effect, it is not easy to form the salicide on the gate poly. Accordingly, the conventional short channel transistor has a problem in that a characteristic of the transistor is deteriorated due to increased gate resistance.
As conventional solutions to overcome this problem, U.S. Pat. No. 6,100,561 discloses a method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation and U.S. Pat. No. 6,214,677 discloses a method of fabricating a self-aligned ultra short channel.